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Researchers at CEA-Leti have presented a new three-step approach to test silicon quantum dot arrays. It represents a new step towards the commercialization of quantum computing based on fabrication methods used in classical computer science.
The research involves testing arrays of floating gate linear quantum dots (QD) fabricated on fully depleted silicon-on-insulator (FDSOI), a substrate also sometimes used in mainstream chip manufacturing.
The first characterization step is performed at room temperature and uses “transistor-like” protocols to collect wafer-level data within hours. This is followed by a longer QD characterization step at less than 2 K. The third step is a template-level qubit manipulation test, which can last for days at 100 mK.
Reclassify exterior gates as entry gates
One of the findings of the test procedure was that within the arrays of QDs, the inner gates provided “state-of-the-art” specifications regarding the threshold voltage (that is when the transistor turns on) and subthreshold slope (how fast the current rises before the threshold voltage is reached).
However, outer gates had more variability due to factors such as doping fluctuations. Dopants are impurities implanted in silicon to increase the electrical conductivity of the silicon. As a solution, the researchers suggested using the outer gates as entry ports rather than for confinement of the QDs.
A second finding was that a so-called split-gate design requires strict overlay control to achieve sufficient symmetry.
Detection of ‘false dots’ at room temperature
As a third recommendation, the researchers developed a room temperature voltage sweep technique that can check for inner port defects. This defectivity is what causes “false points” in the qubit layer and is a major source of yield loss in QD arrays. This means that it causes many defects. Normally, false dots are detected using cryogenic testing, but the room temperature test allows them to be detected earlier.
Finally, by using the FDSOI material, back gates can be fabricated that draw charges away from the interfaces, which is called back biasing. However, the classical method of constructing these gates uses doping implantation, which can cause defects. An alternative method using a TSV-like (through silicon via) metal back gate electrode was proposed.
The research was presented at the VLSI conference in June. “These research findings represent an important step toward addressing the broader silicon spin-qubit integration challenges we discussed at last December’s IEDM conference,” said Heimanu Niebojewski, chief device engineer at CEA- leti. “It’s a very encouraging sign of the maturation of the technology.”